1. Field of the Invention
The present invention relates generally to methods for forming patterned conductor layers within integrated circuits. More particularly, the present invention relates to a masking method employed in forming through a plasma etch method within an integrated circuit a patterned conductor layer from a blanket conductor layer, where the masking method avoids plasma induced electrical discharge damage to integrated circuit structures, such as but not limited to integrated circuit layers and integrated circuit devices, formed beneath the blanket conductor layer.
2. Description of the Related Art
When employing plasma etch methods, such as but not limited to microwave plasma etch methods, reactive ion etch (RIE) plasma etch methods, magnetically enhanced reactive ion etch (MERIE) plasma etch methods and electron cyclotron resonance (ECR) plasma etch methods, for etching a blanket conductor layer to form a patterned conductor layer within an integrated circuit, it is known in the art of integrated circuit fabrication that the blanket conductor layer and any other integrated circuit layers exposed to the plasma etch method will typically become electrically charged incident to exposure of the blanket conductor layer to the plasma employed within the plasma etch method. Blanket conductor layers are typically particularly susceptible to electrical charging within a plasma etch method employed in forming patterned conductor layers from those blanket conductor layers since electrical charge formed upon a blanket conductor layer may be readily concentrated and redistributed over large areas of a blanket conductor layer due to the conductive character of the blanket conductor layer.
While the phenomenon of electrical charge generation within blanket conductor layers incident to patterning those blanket conductor layers to form patterned conductor layers through plasma etch methods is known in the art, the phenomenon of electrical charge generation within blanket conductor layers incident to patterning those blanket conductor layers through plasma etch methods is nonetheless problematic. The phenomenon of electrical charge generation is particularly problematic under circumstances where a patterned conductor layer of narrow linewidth is desired to be formed from a blanket conductor layer. Under such circumstances, the electrical charge generated within the blanket conductor layer becomes exceedingly dense as the blanket conductor layer is patterned to form the narrow linewidth patterned conductor layer. Under circumstances where the narrow linewidth patterned conductor layer so formed adjoins directly or indirectly a dielectric layer or other integrated circuit layer of limited dielectric capacity, an electrical discharge may occur through the dielectric layer or other integrated circuit layer of limited dielectric capacity while patterning the blanket conductor layer to form the narrow linewidth patterned conductor layer. Such an electrical discharge may often damage the dielectric layer, other integrated circuit layer or integrated circuit structures formed beneath the blanket conductor layer.
A particularly common example where damage may occur to an adjoining dielectric layer when patterning a blanket conductor layer to form a patterned conductor layer is encountered when patterning a blanket gate electrode material layer formed upon a blanket gate dielectric layer when forming for use within a field effect transistor (FET) a gate electrode from the blanket gate electrode material layer. A series of schematic cross-sectional diagrams illustrating a proposed mechanism through which such damage may occur is illustrated by reference to FIG. 1 to FIG. 3.
Shown in FIG. 1 is a semiconductor substrate 10 having formed thereupon a blanket gate dielectric layer 12. Formed upon the blanket gate dielectric layer 12 is a partially patterned gate electrode material layer 14 which is being patterned through a plasma etch method employing a plasma 18 and a patterned photoresist layer 16. As is shown in FIG. 1, since the partially patterned gate electrode material layer 14 is formed from a blanket conductor layer, the directions of charge flow and dissipation 20 from the plasma 18 are within the partially patterned gate electrode material layer 14 both towards and away from the patterned photoresist layer 16.
As is shown in FIG. 2, upon further patterning of the partially patterned gate electrode material layer 14 within the plasma 18 there is formed a further partially patterned gate electrode material layer 14'. The further partially patterned gate electrode material layer 14' is of sufficiently limited thickness such that breaks 15 form within the further partially patterned gate electrode material layer 14' forcing plasma induced electrical charge to redistribute within the further partially patterned gate electrode material layer 14' and lead to a direction of charge flow and dissipation 20' from the plasma 18 which is no longer exclusively within the further partially patterned gate electrode material layer 14'. Rather, the direction of charge flow and dissipation 20' from the plasma 18 is sequentially through: (1) the thicker portion of the further partially patterned gate electrode material layer 14' beneath the patterned photoresist layer 16; and (2) the portion of the blanket gate dielectric layer 12 beneath the patterned photoresist layer 16, resulting ultimately in charge flow and dissipation into the semiconductor substrate 10. Under circumstances where substantial quantities of charge flow and are dissipated through the direction of charge flow and dissipation 20' as illustrated in FIG. 2, damage may occur to the portion of the blanket gate dielectric layer 12 formed beneath the patterned photoresist layer 16.
Finally, as is shown in FIG. 3, when the further partially patterned gate electrode material layer 14' has been completely patterned to yield the gate electrode 14a, there is no longer any charge flow and dissipation through the portion of the blanket gate dielectric layer 12 formed beneath the gate electrode 14a and consequently also no additional damage to the portion of the blanket gate dielectric layer 12 formed beneath the gate electrode 14a.
Although FIG. 1 to FIG. 3 illustrate the charges formed incident to patterning the partially patterned gate electrode material layer 14 as positive charges, it is theoretically possible, although in practice typically not preferred, that there may alternatively be formed negative charges within a partially patterned conductor layer, such as the partially patterned gate electrode material layer 14, when the partially patterned conductor layer is patterned to form a patterned conductor layer through a plasma etch method employing a plasma such as the plasma 18. The presence of either positive or negative charges within the partially patterned conductor layer is typically largely determined by the polarity of an electrical bias applied to a semiconductor substrate, such as the semiconductor substrate 10, over which is formed the partially patterned conductor layer, since plasmas employed within plasma etch methods will typically have formed therein substantial quantities of both positive and negative charged species.
Thus, it is towards the goal of limiting within integrated circuits plasma induced electrical discharge damage to integrated circuit structures, such as but not limited to integrated circuit layers and integrated circuit devices, formed beneath blanket conductor layers when those blanket conductor layers are patterned to form patterned conductor layers through plasma etch methods, that the present invention is generally directed.
In that regard, methods through which conductor layers may be modified to provide desired properties within integrated circuits are known in the art of integrated circuit fabrication. For example, Lee in U.S. Pat. No. 5,441,915 discloses a method for fabricating a planarized conductor metallurgy structure for a semiconductor device within an integrated circuit, where the planarized conductor metallurgy structure employs dummy metal lines to fill gaps which would otherwise provide a conductor metallurgy structure which is not readily planarized.
Desirable in the art are methods through which there may be avoided within integrated circuits plasma induced electrical discharge damage to integrated circuit structures, such as but not limited to integrated circuit layers and integrated circuit devices, formed beneath blanket conductor layers when those blanket conductor layers are patterned to form patterned conductor layers through plasma etch methods. Particularly desirable are methods through which there may be avoided plasma induced electrical discharge damage to gate dielectric layers formed beneath blanket gate electrode material layers when those blanket gate electrode material layers are patterned to form gate electrodes through plasma etch methods. It is towards these goals that the present invention is specifically directed.